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FEMTOCLOCKTM CRYSTAL-TO-LVDS CLOCK GENERATOR
ICS844251-14 Features
* * * * * * * *
One differential LVDS output pair Crystal oscillator interface designed for 18pF, parallel resonant crystal (23.2MHz - 30MHz) Output frequency ranges: 145MHz - 187.5MHz and 580MHz - 750MHz VCO range: 580MHz - 750MHz RMS phase jitter at 156.25MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.53ps (typical) Full 3.3V or 2.5V output supply modes 0C to 70C ambient operating temperature Available in lead-free (RoHS 6) package
General Description
The ICS844251-14 is an Ethernet Clock Generator and a member of the HiPerClocksTM family of high HiPerClockSTM performance devices from IDT. The ICS844251-14 uses an 18pF parallel resonant crystal over the range of 23.2MHz - 30MHz. For Ethernet applications, a 25MHz crystal is used. The device has excellent <1ps phase jitter performance, over the 1.875MHz - 20MHz integration range. The ICS844251-14 is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space.
ICS
Common Configuration Table
Inputs Crystal Frequency (MHz) 25 26.67 25 (default) FREQ_SEL 1 1 0 M 25 25 25 N 1 1 4 Multiplication Value M/N 25 25 6.25 Output Frequency Range (MHz) 625 666.67 156.25
Block Diagram
FREQ_SEL
Pulldown
Pin Assignment
VDDA GND XTAL_OUT XTAL_IN 1 2 3 4 8 7 6 5 VDD Q nQ FREQ_SEL
XTAL_IN
OSC
XTAL_OUT
Phase Detector
VCO
580MHz - 750MHz
FREQ_SEL 0 (default) 1
N /4 /1
Q nQ
M = /25 (fixed)
ICS844251-14 8 Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View
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Table 1. Pin Descriptions
Number 1 2 3, 4 5 6, 7 8 Name VDDA GND XTAL_OUT XTAL_IN FREQ_SEL nQ, Q VDD Output Power Input Input Output Power Pulldown Type Description Analog supply pin. Power supply ground. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Frequency select pin. LVCMOS/LVTTL interface levels. Differential output pair. LVDS interface levels. Core supply pin.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol CIN RPULLdown Parameter Input Capacitance Input Pulldown Resistor Test Conditions Minimum Typical 4 51 Maximum Units pF k
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VDD Inputs, VI Outputs, IO Continuos Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG Rating 4.6V -0.5V to VDD + 0.5V 10mA 15mA 129.5C/W (0 mps) -65C to 150C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics, VDD = 3.3V 5%, TA = 0C to 70C
Symbol VDD VDDA IDD IDDA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 VDD - 0.10 Typical 3.3 3.3 Maximum 3.465 VDD 100 10 Units V V mA mA
Table 3B. Power Supply DC Characteristics, VDD = 2.5V 5%, TA = 0C to 70C
Symbol VDD VDDA IDD IDDA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 2.375 VDD - 0.10 Typical 2.5 2.5 Maximum 2.625 VDD 95 10 Units V V mA mA
Table 3C. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V 5% or 2.5V 5%, TA = 0C to 70C
Symbol VIH Parameter Input High Voltage Test Conditions VDD = 3.465V VDD = 2.625V Input Low Voltage Input High Current Input Low Current VDD = 3.465V VDD = 2.625V VDD = VIN = 3.465V or 2.625V VDD = 3.465V or 2.625V, VIN = 0V -5 Minimum 2 1.7 -0.3 -0.3 Typical Maximum VDD + 0.3 VDD + 0.3 0.8 0.7 150 Units V V V V A A
VIL IIH IIL
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Table 3D. LVDS DC Characteristics, VDD = 3.3V 5%, TA = 0C to 70C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change 1.275 Test Conditions Minimum 247 Typical Maximum 454 50 1.525 50 Units mV mV V mV
Table 3E. LVDS DC Characteristics, VDD = VDDA = 2.5V 5%, TA = 0C to 70C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change 1.0 Test Conditions Minimum 247 Typical Maximum 454 50 1.4 50 Units mV mV V mV
Table 4. Crystal Characteristics
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance 23.2 Test Conditions Minimum Typical Fundamental 30 50 7 MHz Maximum Units
pF
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AC Electrical Characteristics
Table 5A. AC Characteristics, VDD = 3.3V 5%, TA = 0C to 70C
Parameter Symbol fOUT Output Frequency Test Conditions FREQ_SEL = 0 FREQ_SEL = 1 156.25MHz, Integration Range: 1.875MHz - 20MHz 625MHz, Integration Range: 1.875MHz - 20MHz 20% to 80% FREQ_SEL = 0 FREQ_SEL = 1 70 48 46 Minimum 145 580 0.53 0.45 550 52 54 Typical Maximum 187.5 750 Units MHz MHz ps ps ps % %
tjit(O)
RMS Phase Jitter, Random; NOTE 1 Output Rise/Fall Time Output Duty Cycle
tR / tF odc
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Please refer to Phase Noise Plots.
Table 5B. AC Characteristics, VDD = 2.5V 5%, TA = 0C to 70C
Parameter Symbol fOUT Output Frequency Test Conditions FREQ_SEL = 0 FREQ_SEL = 1 156.25MHz, Integration Range: 1.875MHz - 20MHz 625MHz, Integration Range: 1.875MHz - 20MHz 20% to 80% FREQ_SEL = 0 FREQ_SEL = 1 70 48 46 Minimum 145 580 0.54 0.45 550 52 54 Typical Maximum 187.5 750 Units MHz MHz ps ps ps % %
tjit(O)
RMS Phase Jitter, Random; NOTE 1 Output Rise/Fall Time Output Duty Cycle
tR / tF odc
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Please refer to Phase Noise Plots.
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Typical Phase Noise at 156.25MHz (3.3V)
Noise Power
dBc Hz
156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.53ps (typical)
Raw Phase Noise Data
Offset Frequency (Hz)
Typical Phase Noise at 625MHz (3.3V)
dBc Hz
Phase Noise Result by adding a Ethernet filter to raw data
Ethernet Filter Ethernet Filter 625MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.45ps Raw Phase Noise Data Noise Power Offset Frequency (Hz)
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Phase Noise Result by adding a Ethernet filter to raw data

ICS844251-14 FEMTOCLOCKTMCRYSTAL-TO-LVDS CLOCK GENERATOR
Parameter Measurement Information
SCOPE
3.3V5% POWER SUPPLY + Float GND -
SCOPE
2.5V5% POWER SUPPLY + Float GND -
VDD VDDA LVDS
Qx
VDD VDDA
Qx
LVDS
nQx
nQx
3.3V LVDS Output Load AC Test Circuit
2.5V LVDS Output Load AC Test Circuit
nQ nQ Q
80%
80% VOD
t PW
t
PERIOD
20%
Q
20% tR tF odc =
t PW t PERIOD
x 100%
Output Rise/Fall Time
Output Duty Cycle/Pulse Width/Period
Phase Noise Plot VDD Noise Power out Phase Noise Mask
DC Input
LVDS
out
VOS/ VOS
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS Phase Jitter
OFFSET VOLTAGE SETUP
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Parameter Measurement Information, continued
VDD

out
DC Input
LVDS
100
VOD/ VOD out
-
DIFFERENTIAL OUTPUT VOLTAGE SETUP
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS844251-14 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and 0.01F bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VDDA pin.
3.3V or 2.5V VDD .01F VDDA .01F 10F 10
Figure 1. Power Supply Filtering
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Crystal Input Interface
The ICS844251-14 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
XTAL_IN C1 27p X1 18pF Parallel Crystal XTAL_OUT C2 27p
Figure 2. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50.
VDD
VDD
R1 Ro Rs 50 0.1f XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
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3.3V, 2.5V LVDS Driver Termination
A general LVDS interface is shown in Figure 4. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input.
3.3V or 2.5V VDD 50
LVDS Driver R1 100
+
-
50
100 Differential Transmission Line
Figure 4. Typical LVDS Driver Termination
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Schematic Example
Figure 5 shows an example of ICS844251-14 application schematic. In this example, the device is operated at VDD = 3.3V. The decoupling capacitor should be located as close as possible to the power pin. The 18pF parallel resonant 25MHz crystal is used. The C1 = 27pF and C2 = 27pF are recommended for frequency accuracy. For different board layouts, the C1 and C2 may be slightly adjusted for optimizing frequency accuracy. For the LVDS output drivers, place a 100 resistor as close to the receiver as possible.
VDD
VDD
R1 10 C3 0.1u
VDDA U1 C4 10u 1 2 3 4 VDDA GND XTAL_OUT XTAL_IN VDD Q nQ FREQ_SEL 8 7 6 5
C5 0.01u Zo = 50 Ohm Q R2 100 Zo = 50 Ohm +
FREQ_SEL
C1 27pF
25 p MHz 18 F
-
X1
nQ
C2 27pF
Logic Input Pin Examples
VDD
Q
Zo = 50 Ohm
Set Logic Input to '1'
RU1 1K
VDD
Set Logic Input to '0'
RU2 Not Install
R3 50
+
To Logic Input pins
RD1 Not Install RD2 1K
To Logic Input pins
nQ
Zo = 50 Ohm
C7 0.1uF R4 50
-
Alternate LVDS Termination
Figure 5. ICS844251-14 Schematic Example
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Power Considerations
This section provides information on power dissipation and junction temperature for the ICS844251-14. Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS844251-14 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (100mA + 10mA) = 381.15mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 129.5.C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.381W *129.5C/W = 119.3C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer).
Table 6. Thermal Resistance JA for 8 Lead TSSOP, Forced Convection
JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 129.5C/W 1 125.5C/W 2.5 123.5C/W
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Reliability Information
Table 7. JA vs. Air Flow Table for a 8 Lead TSSOP
JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 129.5C/W 1 125.5C/W 2.5 123.5C/W
Transistor Count
The transistor count for ICS844251-14 is: 2401
Package Outline and Package Dimensions
Table 8. Package Dimensions Package Outline - G Suffix for 8 Lead TSSOP
All Dimensions in Millimeters Symbol Minimum Maximum N 8 A 1.20 A1 0.5 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 3.10 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 0 8 aaa 0.10 Reference Document: JEDEC Publication 95, MO-153
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Ordering Information
Table 9. Ordering Information
Part/Order Number 844251BG-14 844251BG-14T 844251BG-14LF 844251BG-14LFT Marking 51B14 51B14 1B14L 1B14L Package 8 Lead TSSOP 8 Lead TSSOP "Lead-Free" 8 Lead TSSOP "Lead-Free" 8 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Tube 2500 Tape & Reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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Revision History Sheet
Rev A Table Page 11 Description of Change Added schematic layout. Date 5/1/09
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Contact Information:
www.IDT.com
Sales
800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contact IDT
Technical Support
netcom@idt.com +480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA)
www.IDT.com
(c) 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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